My father once posed a challenging query to me: “Engineers in different industries ask you for circuit advice, and I don’t believe you have practical design experience with each circuit. So, faced with a completely new circuit, how do you actually locate the problem?” At that time, in order to maintain my image, I just smiled and replied, “Ability makes the difference.” What has not been revealed is that I do have a systematic approach. Today, I will share this core methodology, which I have not readily revealed to anyone (including my father), in the hope that it will inspire my fellow engineers.

The core of this methodology lies in the integrated use of five major analysis techniques: equivalent circuits, high-frequency characteristics, transient processes, timing analysis, and engineering calculations. They complement each other and are applicable to the analysis and diagnosis of almost any circuit problem.

Constructing complete equivalent circuits:

Core: The function and interaction of any circuit are realized through the connections between component pins. The internal (e.g., the IC’s input/output stage equivalents) or external (e.g., the parasitic parameters of a discrete device, such as the Cgs of a MOSFET) characteristics of each pin connection collectively define the electrical behavior of that node.

Methodology: The first and fundamental step is to draw an equivalent circuit model of all components connected to the target circuit node or port. This requires an in-depth understanding of the datasheets of the components and their behavioral models under specific conditions.

Incorporate high-frequency characteristics:

Core: Characteristics that are ignored in the DC or low-frequency state can become dominant at high frequencies. This includes:

Parasitic Inductance: Any conductor (wire, PCB trace, pin) that exhibits inductive reactance when subjected to alternating currents.

Distribution capacitance: Any potential difference between conductors separated by an insulating medium (e.g., parallel wires, layers) creates capacitive coupling.

Methodology: The second step is crucial to complement and improve the equivalent circuit model drawn in the first step by explicitly adding these high-frequency related parasitic and distributional parameters. An equivalent circuit containing only ideal components is often ineffective in high-frequency analysis.

Steady-state (DC) operating condition analysis:

Core: Analysis of the behavior of a circuit at a stable operating point (e.g., static bias, logic steady state).

METHODOLOGY: Logic state analysis and basic engineering calculations (e.g., DC bias points, quiescent currents, logic levels, power consumption estimates, etc.) based on equivalent circuits containing the basic components and necessary parasitic parameters. Problems at this stage (e.g., opens, shorts, logic errors, overloads) are usually relatively easy to identify and locate.

In-depth transient process analysis:

Core: Abrupt processes such as circuit startups, shutdowns, signal jumps, switching actions, etc., contain a wealth of information. According to the principle of Fourier analysis, steep rising/falling edges are bound to contain rich high harmonic components.

Methods: This is a key step in diagnosing complex problems. Focus on analyzing the response of the equivalent circuit under transient excitation. At this point, the high-frequency parasitic parameters (inductors, capacitors) incorporated in the second step often become major conflicts, and they can lead to problems such as ringing, overshoots, undershoots, edge degradation, delays, and even oscillations. It is necessary to combine the results of the steady state analysis in the third step and substitute the high-frequency characteristic parameters for the transient simulation or calculation.

Rigorous timing analysis:

Core: In circuits containing high-speed signals, multiple clock domains, control logic, or state machines, strict temporal sequencing between signals is critical. Like a precision dance, a misstep can lead to total failure.

Methodology: Based on the previous analysis (especially transient process analysis), examine the timing relationships between related control signals, data signals, clock signals, enable signals, etc., in terms of setup times, hold times, delays, contention, and risk taking. Identify latent path problems or functional anomalies caused by incorrect signal arrival order or insufficient timing margins.